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ISBN-10: 0738135011

ISBN-13: 9780738135014

Average syntax and semantics for VerilogR HDL-based RTL synthesis are defined during this regular.

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Copyright © 2002 IEEE. All rights reserved. 2 Local parameters—localparam Supported. 11 Name spaces Supported. 38 Copyright © 2002 IEEE. All rights reserved. 1 Operators Supported. See also subclauses that follow. 1 Operators with real operands Not supported. 2 Binary operator precedence Supported. 3 Using integer numbers in expressions Supported. 4 Expression evaluation order Supported. 5 Arithmetic operators The power operator (**) shall be supported only when both operands are constants or if the first operand is 2.

2 Task enabling and argument passing task_enable ::= hierarchical_task_identifier [ ( expression { , expression } ) ] ; Recursion with a static bound shall be supported. 3 Task memory usage and concurrent activation Supported. 1 Function declarations function_declaration ::= function [ automatic ] [ signed ] [range_or_type] function_identifier ; function_item_declaration { function_item_declaration } function_statement endfunction | function [ automatic ] [ signed ] [ range_or_type ] function_identifier ( function_port_list ) ; block_item_declaration { block_item_declaration } function_statement endfunction function_item_declaration ::= block_item_declaration | tf_input_declaration ; function_port_list ::= { attribute_instance } tf_input_declaration { , { attribute_instance } tf_input_declaration } tf_input_declaration ::= input [ reg ] [ signed ] [ range ] list_of_port_identifiers | input [ task_port_type ] list_of_port_identifiers range_or_type ::= range | integer | real | realtime | time block_item_declaration ::= { attribute_instance } block_reg_declaration | { attribute_instance } event_declaration | { attribute_instance } integer_declaration | { attribute_instance } local_parameter_declaration | { attribute_instance } parameter_declaration ; | { attribute_instance } real_declaration | { attribute_instance } realtime_declaration | { attribute_instance } time_declaration block_reg_declaration ::= reg [ signed ] [ range ] list_of_block_variable_identifiers ; list_of_block_variable_identifiers ::= block_variable_type { , block_variable_type } 54 Copyright © 2002 IEEE.

The “value” is not defined by the standard. Examples of “value” are “cla” for +, “wallace” for *. Example 36: assign x = a + (* synthesis, implementation = "ripple" *) b; NOTE—The implementation is only a recommendation to the synthesis tool. 5 Keep attribute The syntax is: (* synthesis, keep [ = ] *) This attribute shall apply to a net, reg or a module instance or to a module. With the presence of this attribute on an instance or module, the instance or module shall be preserved, and not deleted nor replicated, even if the outputs of the module are not connected.

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1364.1-2002 IEEE Standard for Verilog Register Transfer Level Synthesis


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